The present invention claims the benefit of Korean Patent Application No. P2001-38131 filed in Korea on Jun. 29, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a circuit for testing a ferroelectric capacitor in a ferroelectric random access memory (FRAM) which measures variations of a current and a voltage at the ferroelectric capacitor in the FRAM for providing an accurate ferroelectric model parameter.
2. Background of the Invention
The FRAM, having in general a data processing speed similar to a DRAM(Dynamic Random Access Memory), and being capable of conserving data even if the power is turned off, is paid attention as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
A related art FRAM will be explained, with reference to the attached drawings. FIG. 1 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to FIG. 1, it can be known that a polarization induced by an electric field is, not erased totally, but, a certain amount(xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) of which is remained, even if the electric field is removed owing to existence of the residual polarization(or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states are corresponded to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 respectively in application to a memory.
FIG. 2 illustrates a basic sawyer tower circuit.
Referring to FIG. 2, the sawyer tower has a sense capacitor connected to the ferroelectric capacitor which is an object of measurement in series. In order to make an accurate measurement of voltage variation at the ferroelectric capacitor, a capacitance of the sense capacitor is made great for inducing most of voltage drop at the ferroelectric capacitor. Because a small sized sense capacitor is not adequate to measure the voltage drop at the ferroelectric capacitor. A drive voltage is applied to a drive terminal, and the voltage drop at the ferroelectric capacitor is measured at both electrode terminals of the sense capacitor. That is, voltages at the both electrodes of the sense capacitor are sensed, to detect a voltage change at the ferroelectric capacitor.
FIG. 3 illustrates a block diagram showing a measuring apparatus, measuring cable, and a measuring device with a probe.
Referring to FIG. 3, a measured signal is received at the measuring apparatus through a return terminal, wherein the measured signal is delayed due to a parasitic capacitance and/or a parasitic resistance at the return terminal, and distorted as the measured signal is exposed to noise sources. Therefore, there is a limitation in fast speed measuring a voltage variation of the ferroelectric capacitor.
However, the related art circuit for testing a ferroelectric capacitor in a FRAM has the following problems.
For obtaining accurate modeling parameters of a ferroelectric capacitor in a FRAM, measurements of ferroelectric capacitor characteristics should be possible. In the meantime, the ferroelectric capacitor has very great time dependences on phenomena, such as degradation, and relaxation, and the like, caused by imprint, and fatigue, etc., to exhibit characteristic variations even within a minute time period. The related art circuit for measuring a ferroelectric capacitor has limitations in a capacitor size, or a measuring time period due to noise sources affecting the return terminal. There has been no device that can measure such time dependences on degradation, relaxation, and the like accurately yet, and, with respect to a measurable capacitor size, measurement of a memory of a cell size level is not possible, but measurement of a memory of only a large size level is possible. Therefore, it is difficult to provide model parameters having accurate ferroelectric characteristics reflected thereto.
Accordingly, the present invention is directed to a circuit for testing a ferroelectric capacitor in a ferroelectric random access memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for testing a ferroelectric capacitor in a ferroelectric random access memory, which can measure variations of current and voltage at a ferroelectric capacitor in an FRAM, for providing accurate ferroelectric model parameters.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a circuit for testing a ferroelectric capacitor in a ferroelectric random access memory (FRAM) for storing a data at the ferroelectric capacitor includes a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor, a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal, an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal, a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal, a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit count output within a specific period, an input drive control part for receiving the reference voltage signal, a voltage signal at the first electrode of the ferroelectric capacitor, the measuring control signal, the write pulse bar signal, and applying a driving voltage to a second electrode of the ferroelectric capacitor in response to the test pulse signal, and a measured result forwarding part for receiving the reference voltage signal, and the voltage signal from the first electrode at a non-inversion terminal, and an inversion terminal thereof respectively, and amplifying, and forwarding a voltage variation between the electrodes of the ferroelectric capacitor.
In another aspect, a circuit for testing a ferroelectric capacitor in an FRAM for storing data in the ferroelectric capacitor includes a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor, a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal, an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal, a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal, a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit output within a specific period, an input drive control part for receiving the reference voltage signal, a voltage signal of the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and providing a drive voltage to a second electrode of the ferroelectric capacitor in response to the test pulse signal, a measured result forwarding part for receiving the reference voltage signal, and the voltage signal from the first electrode at a non-inversion terminal, and an inversion terminal thereof respectively, and amplifying, and forwarding a voltage variation between the electrodes of the ferroelectric capacitor, and a sense capacitor connected between the first electrode of the ferroelectric capacitor, and the measured result forwarding part for sensing voltage variation of the ferroelectric capacitor.
In another aspect, a circuit for testing a ferroelectric capacitor in an FRAM for storing data in the ferroelectric capacitor includes a test pulse signal generating part for generating a test pulse signal for measuring variation of charge in the ferroelectric capacitor, a test pulse providing part for digitizing the test pulse signal by using a reference voltage signal to provide a digital test pulse signal, an n-bit counter for making a 2n clock counting per a cycle in response to the digital test pulse signal as a clock signal, a measuring control signal providing part for subjecting count outputs for each bit, and the digital test pulse signal to logic operation, to provide a measuring control signal, a write pulse bar signal generating part for generating a write pulse bar signal in correspondence to a specific bit output within a specific period, an input drive control part for receiving the reference voltage signal, a voltage signal of the first electrode of the ferroelectric capacitor, the measuring control signal, and the write pulse bar signal, and providing a drive voltage to a second electrode of the ferroelectric capacitor in response to the test pulse signal, a measured result forwarding part for receiving the reference voltage signal, and the voltage signal from the first electrode at a non-inversion terminal, and an inversion terminal thereof respectively, and amplifying, and forwarding a voltage variation between the electrodes of the ferroelectric capacitor, and a sense resistor connected between the non-inversion terminal, and the inversion terminal of the amplification part.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.